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IS61LV256
IS61LV256
32K x 8 LOW VOLTAGE CMOS STATIC RAM
ISSI
(R) ISSI
(R)
FEBRUARY 1996
FEATURES
* High-speed access time: 12, 15, 20, 25 ns * Automatic power-down when chip is deselected * CMOS low power operation -- 345 mW (max.) operating -- 7 mW (max.) CMOS standby * TTL compatible interface levels * Single 3.3V power supply * Fully static operation: no clock or refresh required * Three-state outputs
DESCRIPTION The ISSI IS61LV256 is a very high-speed, low power, 32,768-word by 8-bit static RAM. It is fabricated using ISSI's
high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 12 ns maximum. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 50 W (typical) with CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Enable (CE). The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61LV256 is available in the JEDEC standard 28-pin, 300-mil DIP and SOJ, plus the 450-mil TSOP package.
FUNCTIONAL BLOCK DIAGRAM
A0-A14
DECODER
256 X 1024 MEMORY ARRAY
VCC GND I/O DATA CIRCUIT
I/O0-I/O7
COLUMN I/O
CE OE WE CONTROL CIRCUIT
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 1996, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
Rev. F 0296 SR81995LV61
2-1
IS61LV256
PIN CONFIGURATION
28-Pin DIP and SOJ
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
ISSI
PIN CONFIGURATION
28-Pin TSOP
(R)
OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3
22 23 24 25 26 27 28 1 2 3 4 5 6 7
21 20 19 18 17 16 15 14 13 12 11 10 9 8
A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2
PIN DESCRIPTIONS
A0-A14 Address Inputs Chip Enable Input Output Enable Input Write Enable Input Input/Output Power Ground
TRUTH TABLE
Mode Not Selected (Power-down) Output Disabled Read Write
WE
X H H L
CE
H L L L
OE
X H L X
I/O Operation High-Z High-Z DOUT DIN
Vcc Current ISB1, ISB2 ICC1, ICC2 ICC1, ICC2 ICC1, ICC2
CE OE WE
I/O0-I/O7 Vcc GND
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM TBIAS TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current (LOW) Value -0.5 to +4.6 -55 to +125 -65 to +150 0.5 20 Unit V C C W mA
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2-2
Integrated Silicon Solution, Inc.
Rev. F 0296 SR81995LV61
IS61LV256
OPERATING RANGE
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V +10%, -5% 3.3V 5%
ISSI
(R)
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter VOH VOL VIH VIL ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage GND VIN VCC GND VOUT VCC, Outputs Disabled Com. Ind. Com. Ind. Test Conditions VCC = Min., IOH = -2.0 mA VCC = Min., IOL = 4.0 mA Min. 2.4 -- 2.2 -0.3 -2 -5 -2 -5 Max. -- 0.4 VCC + 0.3 0.8 2 5 2 5 Unit V V V V A A
Notes: 1. VIL = -3.0V for pulse width less than 10 ns. 2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter ICC1 ICC2 ISB1 Vcc Operating Supply Current Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., CE = VIL IOUT = 0 mA, f = 0 VCC = Max., CE = VIL IOUT = 0 mA, f = fMAX VCC = Max., VIN = VIH or VIL CE VIH, f = 0 Com. Ind. Com. Ind. Com. Ind. Com. Ind. -12 ns Min. Max. -- -- -- -- -- -- -- -- 50 -- 100 -- 10 -- 2 -- -15 ns Min. Max. -- -- -- -- -- -- -- -- 50 60 90 100 10 20 2 5 -20 ns Min. Max. -- -- -- -- -- -- -- -- 50 60 80 90 10 20 2 5 -25 ns Min. Max. -- -- -- -- -- -- -- -- 50 60 70 80 10 20 2 5 Unit mA mA mA
ISB2
CE VCC - 0.2V,
VCC = Max.,
mA
VIN > VCC - 0.2V, or VIN 0.2V, f = 0
Notes: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE(1,2)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 5 Unit pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 3.3V.
Integrated Silicon Solution, Inc.
Rev. F 0296 SR81995LV61
2-3
IS61LV256
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter Read Cycle Time Address Access Time Output Hold Time -12 ns Min. Max. 12 -- 2 -- -- 0 -- 3 -- 0 -- -- 12 -- 12 6 -- 7 -- 5 -- 13 -15 ns Min. Max. 15 -- 2 -- -- 0 -- 3 -- 0 -- -- 15 -- 15 7 -- 8 -- 6 -- 15 -20 ns Min. Max. 20 -- 2 -- -- 0 -- 3 -- 0 -- -- 20 -- 20 8 -- 9 -- 9 -- 18 -25 ns Min. Max. 25 -- 2 -- -- 0 -- 3 -- 0 -- -- 25 -- 25 9 -- 10 -- 10 -- 20
ISSI
Unit ns ns ns ns ns ns ns ns ns ns ns
(R)
tRC tAA tOHA tACE tDOE tLZOE(2) tHZOE tLZCE tPU(3) tPD
(3) (2) (2)
tHZCE(2)
CE Access Time OE Access Time OE to Low-Z Output OE to High-Z Output CE to Low-Z Output CE to High-Z Output CE to Power-Up CE to Power-Down
Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested.
AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1a and 1b
AC TEST LOADS
635 3.3V
635 3.3V
OUTPUT 30 pF Including jig and scope 702
OUTPUT 5 pF Including jig and scope 702
Figure 1a.
Figure 1b.
2-4
Integrated Silicon Solution, Inc.
Rev. F 0296 SR81995LV61
IS61LV256
AC WAVEFORMS READ CYCLE NO. 1(1,2)
ISSI
(R)
tRC
ADDRESS
tAA tOHA tOHA
DATA VALID
DOUT
READ CYCLE NO. 2(1,3)
tRC
ADDRESS
tAA tOHA
OE
tDOE tHZOE
CE
tACE tLZCE
tLZOE
tHZCE
DATA VALID
DOUT
HIGH-Z
tPU
tPD
50% 50%
ICC
SUPPLY CURRENT
ISB
Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions.
Integrated Silicon Solution, Inc.
Rev. F 0296 SR81995LV61
2-5
IS61LV256
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol Parameter Write Cycle Time -12 ns Min. Max. 12 8 8 0 0 8 6 0 -- 0 -- -- -- -- -- -- -- -- 6 -- -15 ns Min. Max. 15 10 10 0 0 10 8 0 -- 0 -- -- -- -- -- -- -- -- 7 -- -20 ns Min. Max. 20 13 15 0 0 13 10 0 -- 0 -- -- -- -- -- -- -- -- 8 -- -25 ns Min. Max. 25 15 20 0 0 15 12 0 -- 0 -- -- -- -- -- -- -- -- 10 --
ISSI
(R)
Unit ns ns ns ns ns ns ns ns ns ns
tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE(2) tLZWE
(2) (4)
CE to Write End
Address Setup Time to Write End Address Hold from Write End Address Setup Time
WE Pulse Width
Data Setup to Write End Data Hold from Write End
WE LOW to High-Z Output WE HIGH to Low-Z Output
Notes: 1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 4. Tested with OE HIGH.
AC WAVEFORMS
WE WRITE CYCLE NO. 1 (WE Controlled)(1,2)
tWC
ADDRESS
tSCE tHA
CE
tAW
WE
tSA tHZWE
tPWE tLZWE
HIGH-Z
DOUT
DATA UNDEFINED
tSD
tHD
DIN
DATA-IN VALID
2-6
Integrated Silicon Solution, Inc.
Rev. F 0296 SR81995LV61
IS61LV256
WRITE CYCLE NO. 2 (CE Controlled)(1,2) CE
tWC
ISSI
(R)
ADDRESS
tSA tSCE tHA
CE
tAW tPWE
WE
tHZWE tLZWE
HIGH-Z
DOUT
DATA UNDEFINED
tSD
tHD
DIN
DATA-IN VALID
Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE VIH.
ORDERING INFORMATION Commercial Range: 0C to +70C
Speed (ns) 12 12 12 15 15 15 20 20 20 25 25 25 Order Part No. IS61LV256-12N IS61LV256-12T IS61LV256-12J IS61LV256-15N IS61LV256-15T IS61LV256-15J IS61LV256-20N IS61LV256-20T IS61LV256-20J IS61LV256-25N IS61LV256-25T IS61LV256-25J Package 300-mil Plastic DIP TSOP - 450 mil 300-mil Plastic SOJ 300-mil Plastic DIP 450-mil TSOP 300-mil Plastic SOJ 300-mil Plastic DIP 450-mil TSOP 300-mil Plastic SOJ 300-mil Plastic DIP 450-mil TSOP 300-mil Plastic SOJ
ORDERING INFORMATION Industrial Range: -40C to +85C
Speed (ns) 12 12 12 15 15 15 20 20 20 25 25 25 Order Part No. IS61LV256-12NI IS61LV256-12TI IS61LV256-12JI IS61LV256-15NI IS61LV256-15TI IS61LV256-15JI IS61LV256-20NI IS61LV256-20TI IS61LV256-20JI IS61LV256-25NI IS61LV256-25TI IS61LV256-25JI Package 300-mil Plastic DIP TSOP - 450 mil 300-mil Plastic SOJ 300-mil Plastic DIP 450-mil TSOP 300-mil Plastic SOJ 300-mil Plastic DIP 450-mil TSOP 300-mil Plastic SOJ 300-mil Plastic DIP 450-mil TSOP 300-mil Plastic SOJ
Integrated Silicon Solution, Inc.
Rev. F 0296 SR81995LV61
2-7
IS61LV256
ISSI
(R)
ISSI
(R)
Integrated Silicon Solution, Inc.
680 Almanor Avenue Sunnyvale, CA 94086 Fax: (408) 245-4774 Toll Free: 1-800-379-4774 http://www.issiusa.com
2-8
Integrated Silicon Solution, Inc.
Rev. F 0296 SR81995LV61

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